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Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADP2323
PGOOD1
SCFG
1
2
24
23
SW1
BST1
SYNC
GND
INTVCC
RT
MODE
PGOOD2
3
4
5
6
7
8
ADP2323
TOP VIEW
(Not to Scale)
22
21
20
19
18
17
DL1
PGND
VDRV
DL2
BST2
SW2
NOTES
1. THE EXPOSED PAD SHOULD BE SOLDERED TO AN EXTERNAL GND PLANE.
Figure 4. Pin Configuration (Top View)
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14, 15
16, 17
18
19
20
21
22
Mnemonic
PGOOD1
SCFG
SYNC
GND
INTVCC
RT
MODE
PGOOD2
FB2
COMP2
SS2
TRK2
EN2
PVIN2
SW2
BST2
DL2
VDRV
PGND
DL1
Description
Power-Good Output (Open Drain) for Channel 1. A pull-up resistor of 10 kΩ to 100 kΩ is recommended.
Synchronization Configuration Input. The SCFG pin configures the SYNC pin as an input or output. Connect
SCFG to INTVCC to configure SYNC as an output. Using a resistor to pull down to GND configures SYNC as an
input with various phase shift degrees.
Synchronization. This pin can be configured as an input or an output. When configured as an output, it
provides a clock at the switching frequency. When configured as an input, this pin accepts an external clock
to which the regulators are synchronized and the phase shift is configured by SCFG. Note that when SYNC is
configured as an input, the PFM mode is disabled and the device works only in continuous conduction mode
(CCM).
Analog Ground. Connect to the ground plane.
Internal 5 V Regulator Output. The IC control circuits are powered from this voltage. Place a 1 μF ceramic
capacitor between INTVCC and GND.
Connect a resistor between RT and GND to program the switching frequency between 250 kHz and 1.2 MHz.
Mode Selection. When this pin is connected to INTVCC, the PFM mode is disabled and the regulator works
only in CCM. When this pin is connected to ground, the PFM mode is enabled. If the low-side device is a
diode, the MODE pin must be connected to ground.
Power-Good Output (Open Drain) for Channel 2. A pull-up resistor of 10 kΩ to 100 kΩ is recommended.
Feedback Voltage Sense Input for Channel 2. Connect to a resistor divider from the Channel 2 output voltage,
V OUT2 . Connect FB2 to INTVCC for parallel applications.
Error Amplifier Output for Channel 2. Connect an RC network from COMP2 to GND. Connect COMP1 and
COMP2 together for parallel applications.
Soft Start Control for Channel 2. Connect a capacitor from SS2 to GND to program the soft start time. For
parallel applications, SS2 remains open.
Tracking Input for Channel 2. To track a master voltage, drive this pin from a voltage divider from the master
voltage. If the tracking function is not used, connect TRK2 to INTVCC.
Enable Pin for Channel 2. An external resistor divider can be used to set the turn-on threshold. When not
using the enable pin, connect EN2 to PVIN2.
Power Input for Channel 2. Connect PVIN2 to the input power source, and connect a bypass capacitor
between PVIN2 and ground.
Switch Node for Channel 2.
Supply Rail for the Gate Drive of Channel 2. Place a 0.1 μF capacitor between SW2 and BST2.
Low-Side Gate Driver Output for Channel 2. Connect a resistor between DL2 and PGND to program the
current-limit threshold of Channel 2.
Low-Side Driver Supply Input. Connect VDRV to INTVCC. Place a 1 μF ceramic capacitor between the VDRV
pin and PGND.
Driver Power Ground. Connect to the source of the synchronous N-channel MOSFET.
Low-Side Gate Driver Output for Channel 1. Connect a resistor between this pin and PGND to program the
current-limit threshold of Channel 1.
Rev. A | Page 7 of 32
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